A. Uran, Y. Leblebici, A. Emami and V. Cevher, “ An AC-Coupled Wideband Neural Recording Front-End With Sub-1mm2×fJ/conv-step Efficiency and 0.97 NEF”, in IEEE Solid-State Circuits Letters, DOI: 10.1109/LSSC.2020.3013993.

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B. A. Haghi, S. Kellis, S. Shah, M. Ashok, L. Bashford, D. Kramer, B. Lee, Ch. Liu, R. A. Andersen, and A. Emami, “ Deep Multi-State Dynamic Recurrent Neural Networks Operating on Wavelet Based Neural Features for Robust Brain Machine Interfaces”, 2019 Thirty-third Conference on Neural Information Processing Systems (NeurIPS 2019), 2019, Vancouver, Canada.

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B. Haghi, S. Kellis, M. Ashok, S. Shah, L. Bashford, D. Kramer, B. Lee, C. Liu, R. Andersen, A. Emami, “ Deep multi-state dynamic recurrent neural networks for robust brain-machine interfaces”, Program No. 406.04. 2019 Neuroscience Meeting Planner. Chicago, IL: Society for Neuroscience, 2019. Online.

Abstract

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Sahil Shah, Benyamin Haghi, Spencer Kellis, Luke Bashford, Daniel Kramer, Brian Lee, Charles Liu, Richard Andersen, and Azita Emami “Decoding Kinematics from Human Parietal Cortex using Neural Networks“ IEEE EMBS Conference on Neural Engineering 2019.

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Benyamin Haghi, Spencer Kellis, Luke Bashford, Sahil Shah,Daniel Kramer, Brian Lee, Charles Liu, Richard Andersen, and Azita Emami “Robust Learning Algorithms For Brain Machine Interfaces” IEEE Brain Initiative Workshop on Advanced NeuroTechnologies, 2018

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Milad Taghavi, Benyamin A. Haghi, Masoud Farivar, Mahsa Shoaran, Azita Emami, “A 41.2 nJ/class, 32-Channel On-Chip Classifier for Epileptic Seizure Detection”  Annual International Conference of theIEEE Engineering in Medicine and Biology Society (EMBC), 2018

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Mahsa Shoaran, Benyamin A. Haghi, Milad Taghavi, Masoud Farivar, Azita Emami, “Energy-Efficient Classification for Resource-Constrained Biomedical Applications” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2018.

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Taige Wang, Mahsa Shoaran, Azita Emami, “Towards Adaptive Deep Brain Stimulation in Parkinson’s Disease: LFP-based Feature Analysis and Classification,” IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), 2018.

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M. Shoaran, B. A. Haghi, M. Farivar, A. Emami, “Efficient Feature Extraction and Classification Methods in Neural Interfaces,” The BRIDGE Magazine, National Academy of Engineering, winter 2017 edition

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M. Shoaran, M. Farivar, A. Emami, “Hardware-Friendly Seizure Detection with a Boosted Ensemble of Shallow Decision Trees,” International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), Aug. 2016

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M. Shoaran, M. Shahshahani, M. Farivar, J. Almajano, A. Shahshahani, A. Schmid, A. Bragin, Y. Leblebici, A. Emami, “A 16-Channel 1.1mm² Implantable Seizure Control SoC with Sub-μW/Channel Consumption and Closed-Loop Stimulation in 0.18μm CMOS,” IEEE Symposium on VLSI Circuits, June 2016

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K. C. Chen, W. Kuo, A. Emami, “A 60-Gb/s PAM4 Wireline Receiver with 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS”, IEEE Custom Integrated Circuits Conference (CICC), Mar. 2020

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Kuan-Chang Chen and Azita Emami, “ A 25-Gb/s Avalanche Photodetector-Based Burst-Mode Optical Receiver With 2.24-ns Reconfiguration Time in 28-nm CMOS”, IEEE Journal of Solid-State Circuits, vol. 54, no. 6, pp. 1682-1693, June 2019

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Kuan-Chang Chen and Azita Emami, “ A 25Gb/s APD-Based Burst-Mode Optical Receiver with 2.24ns Reconfiguration Time in 28nm CMOS”, IEEE Custom Integrated Circuits Conference (CICC) 2018.

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A. Emami, “Optical Interconnects: Design and Analysis,” invited paper at the Optical Fiber Communication Conference (OFC), OSA Technical Digest (online) (Optical Society of America, 2017), paper W4I.1.

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Mayank Raj, Saman Saeedi, Azita Emami “A Wideband Injection Locked Quadrature Clock Generation and Distribution Technique for an Energy-Proportional 16–32 Gb/s Optical Receiver in 28 nm FDSOI CMOS,” IEEE Journal of Solid-State Circuits, vol.51, no.10, pp.2446 – 2462, Oct. 2016.

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Mayank Raj, Manuel Monge, Azita Emami “A Modelling and Nonlinear Equalization Technique for a 20 Gb/s 0.77 pJ/b VCSEL Transmitter in 32 nm SOI CMOS,” IEEE Journal of Solid-State Circuits, vol.51, no.8, pp.1734 – 1743, July. 2016

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Saman Saeedi, Azita Emami “A 10Gb/s, 342fJ/bit Micro-Ring Modulator Transmitter with Switched-Capacitor Pre-Emphasis and Monolithic Temperature Sensor in 65nm CMOS,” IEEE Symposium on VLSI Circuits, June 2016

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S. Saeedi, S. Menezo, G. Pares, A. Emami, “A 25Gb/s 3D-Integrated CMOS/Silicon-Photonic Receiver for Low-Power High-Sensitivity Optical Communication,” IEEE Journal of Lightwave Technology, 2015.

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M. Raj, M. Monge, A. Emami, “A 20Gb/s 0.77pJ/b VCSEL Transmitter with Nonlinear Equalization in 32nm SOI CMOS“, IEEE Custom Integrated Circuits Conference (CICC), 2015 (Best Student Paper Award-Second Place.)

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S. Saeedi, B. Abiri, A. Hajimiri, A. Emami, “Differential Optical Ring Modulator: Breaking the Bandwidth/Quality-factor Trade-off“, 41st European Conference on Optical Communication (ECOC) , IEEE, 2015.

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S. Saeedi, A. Emami, “Silicon-photonic PTAT temperature sensor for micro-ring resonator thermal stabilization,” Optics Express, vol.23, no.17, pp.21875-21883, Aug. 2015.

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S. Saeedi, A. Emami, “Silicon-photonic PTAT temperature sensor for micro-ring resonator thermal stabilization,” IEEE European Conference on Optical Communication (ECOC), 2015.

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S. Saeedi, S. Menezo and A. Emami, “A 25Gbps 3D-Integrated CMOS/Silicon Photonic Optical Receiver with -15dBm Sensitivity and 0.17pJ/bit Energy Efficiency“, IEEE Optical Interconnect Conference (OIC), 2015

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M. Raj, S. Saeedi, A. Emami, “A 4-to-11GHz Injection-Locked Quarter-Rate Clocking for an Adaptive 153fJ/b Optical Receiver in 28nm FDSOI CMOS“, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2015

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S. Saeedi, A. Emami, “A 25Gb/s 170μW/Gb/s High-Sensitivity Optical Receiver in 28nm CMOS for Low-power Optical Communication“, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2014.

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M. Honarvar, A. Emami-Neyestanak, “24-Gb/s Double-Sampling Receiver for Ultra-Low-Power Optical Communication,” IEEE Journal of Solid-State Circuits, vol.48, no.2, pp.344-357, Feb. 2013.

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M. Honarvar, A. Emami-Neyestanak, “Ultra Low-Power Receiver Design for Dense Optical Interconnects“, IEEE Optical Interconnects Conference (OIC), vol., no., pp.115-116, 20-23 May 2012.

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M. Honarvar, A. Emami-Neyestanak, “An 18.6Gb/s Double-Sampling Receiver in 65nm CMOS for Ultra Low-power Optical Communication“, International Solid-State Cicruits Conference (ISSCC), 2012.

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S. Palermo, A. Emami-Neyestanak, M. Horowitz, “A 90nm CMOS 16Gb/sTransceiver for Optical Interconnects“, IEEE Journal of Solid-State Circuits, vol.43, no.5, pp.1235-1246, May 2008.

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S. Palermo, A. Emami-Neyestanak, M. Horowitz, “A 90nm CMOS 16Gb/s Transceiver for Optical Interconnects“, IEEE International Solid-State Circuits Conference (ISSCC), Digest of tech. papers, 2007.

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D. Miller, A. Bhatnagar, S. Palermo, A. Emami-Neyestanak, M. Horowitz, “Opportunities for Optics in Integrated Circuits Application“, IEEE International Solid-State Circuits Conference (ISSCC), 2005.

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A. Emami-Neyestanak, S. Palermo, H. Lee and M. Horowitz, “CMOS Transceiver with Baud Rate Clock Recovery for Optical Interconnects“, IEEE Symposium on VLSI Circuits, June 2004.

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A. Emami-Neyestanak, D. Liu, G. Keeler, N. Helman and M. Horowitz, “A 1.6 Gbps, 3mW CMOS Receiver for Optical Communication“, IEEE Symposium on VLSI Circuits, June 2002, pages 84-8.

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M. Honarvar, A. Emami-Neyestanak, “A 20GB/s 136fJ/b 12.5Gb/s/μm On-Chip Link in 28nm CMOS“, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), vol., no., 2-4 June 2013

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M. Honarvar, A. Emami-Neyestanak, “A 15-Gb/s 0.5-mW/Gbps Two-Tap DFE Receiver With Far-End Crosstalk Cancellation“, IEEE Journal of Solid-State Circuits, vol.47, no.10, pp.2420-2432, Oct. 2012

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M. Honarvar, A. Emami-Neyestanak, “A Low-Power 20Gb/s Transmitter in 65nm CMOS Technology“, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), vol., no., pp.149-152, 17-19 June 2012

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M. Honarvar, A. Emami-Neyestanak, “A 15Gb/s 0.5mW/Gb/s 2-Tap DFE Receiver with Far-End Crosstalk Cancellation“, International Solid-State Cicruits Conference (ISSCC), 2011

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M. Loh, A. Emami, “All-Digital CDR for High-Density, High-Speed I/O“, IEEE Symposium on VLSI Circuits, 2010

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A. Emami-Neyestanak, A. Varzaghani, J. Bulzacchelli, A. Rylyakov, C.-K.K. Yang, D. Friedman, “A Low-Power Receiver with Switched-Capacitor Summation DFE” IEEE Symposium on VLSI Circuits, Digest of tech. papers, 2006

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A. Emami-Neyestanak, A. Varzaghani, J. Bulzacchelli, A. Rylyakov, C.-K.K. Yang and Daniel Friedman “A 6.0 mW, 10.0 Gb/s Receiver with Switched-Capacitor Summation DFE,”(Invited) IEEE Journal of Solid-State Circuits, vol.42, no.4, pp.889-896, April 2007

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Mayank Raj, Saman Saeedi, Azita Emami “A Wideband Injection Locked Quadrature Clock Generation and Distribution Technique for an Energy-Proportional 16–32 Gb/s Optical Receiver in 28 nm FDSOI CMOS,” IEEE Journal of Solid-State Circuits, vol.51, no.10, pp.2446 – 2462, Oct. 2016.

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S. Saeedi, A. Emami, “An 8GHz First-order Frequency Synthesizer for Low-Power On-Chip Clock Generation“, IEEE Journal of Solid-state Circuits, vol. 50, no. 8, pp. 1848-1860, Aug. 2015

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M. Raj, S. Saeedi, A. Emami, “A 4-to-11GHz Injection-Locked Quarter-Rate Clocking for an Adaptive 153fJ/b Optical Receiver in 28nm FDSOI CMOS“, IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2015

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M. Raj, A. Emami, “A Wideband Injection Locking Scheme and Quadrature Phase Generation in 65nm CMOS,”(Invited) IEEE Transactions on Microwave Theory and Techniques, vol.62, no.4, pp.763-772, Apr. 2014

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S. Saeedi, A. Emami, “An 8GHz First-order Frequency Synthesizer based on Phase Interpolation and Quadrature Frequency Detection in 65nm CMOS“, IEEE Custom Integrated Circuits Conference (CICC), 2014

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M. Raj, A. Emami-Neyestanak, “A Wideband Injection Locking Scheme and Quadrature Phase Generation in 65nm CMOS“, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), vol., no., 2-4 June 2013

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M. Loh, A. Emami-Neyestanak, “A 3×9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O“, IEEE Journal of Solid-State Circuits, vol.47, no.3, March 2012

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M. Loh, A. Emami, “All-Digital CDR for High-Density, High-Speed I/O“, IEEE Symposium on VLSI Circuits, 2010

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S. Palermo, A. Emami-Neyestanak, M. Horowitz, “A 90nm CMOS 16Gb/sTransceiver for Optical Interconnects“, IEEE Journal of Solid-State Circuits, vol.43, no.5, pp.1235-1246, May 2008

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A. Emami-Neyestanak, S. Palermo, H. Lee and M. Horowitz, “CMOS Transceiver with Baud Rate Clock Recovery for Optical Interconnects“, IEEE Symposium on VLSI Circuits, June 2004

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J. Yoo, C. Turnes, E. Nakamura, C. Le, S. Becker, E. Sovero, M. Wakin, M. Grant, J. Romberg, A. Emami-Neyestanak, and E. Candès, “A Compressed Sensing Parameter Extraction Platform for Radar Pulse Signal Acquisition“, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol.2, no.3, pp.626-638, Sept. 2012

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M. Wakin, S. Becker, E. Nakamura, M. Grant, E. Sovero, D. Ching, J. Yoo, J. Romberg, A. Emami-Neyestanak, and E. Candès, “A Nonuniform Sampler for Wideband Spectrally-Sparse Environments“, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol.2, no.3, pp.516-529, Sept. 2012

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J. Yoo, S. Becker, M. Loh, M. Monge, E. Candès, A. Emami-Neyestanak, “A 100MHz-2GHz 12.5x sub-Nyquist Rate Receiver in 90nm CMOS“, IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2012

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J. Yoo, S. Becker, M. Loh, M. Monge, E. Candès, A. Emami-Neyestanak, “Design and Implementation of a Fully Integrated Compressed-Sensing Signal Acquisition System“, IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), 2012

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J. Yoo, A. Khajehnejad, B. Hassibi, A. Emami-Neyestanak “An Analog Sub-Linear Time Sparse Signal Acquisition Framework Based on Structured Matrices“, IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), 2012

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